tests/configs/memtest-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2010 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
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   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
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  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Ron Dreslinski
  29
  30 import m5
  31 from m5.objects import *
  32 from m5.defines import buildEnv
  33 from m5.util import addToPath
  34 import os, optparse, sys
  35
  36 # Get paths we might need
  37 config_path = os.path.dirname(os.path.abspath(__file__))
  38 config_root = os.path.dirname(config_path)
  39 m5_root = os.path.dirname(config_root)
  40 addToPath(config_root+'/configs/common')
  41 addToPath(config_root+'/configs/ruby')
  42 addToPath(config_root+'/configs/topologies')
  43
  44 import Ruby
  45 import Options
  46
  47 parser = optparse.OptionParser()
  48 Options.addCommonOptions(parser)
  49
  50 # Add the ruby specific and protocol specific options
  51 Ruby.define_options(parser)
  52
  53 (options, args) = parser.parse_args()
  54
  55 #
  56 # Set the default cache size and associativity to be very small to encourage
  57 # races between requests and writebacks.
  58 #
  59 options.l1d_size="256B"
  60 options.l1i_size="256B"
  61 options.l2_size="512B"
  62 options.l3_size="1kB"
  63 options.l1d_assoc=2
  64 options.l1i_assoc=2
  65 options.l2_assoc=2
  66 options.l3_assoc=2
  67
  68 #MAX CORES IS 8 with the fals sharing method
  69 nb_cores = 8
  70
  71 # ruby does not support atomic, functional, or uncacheable accesses
  72 cpus = [ MemTest(atomic=False, percent_functional=50,
  73                  percent_uncacheable=0, suppress_func_warnings=True) \
  74          for i in xrange(nb_cores) ]
  75
  76 # overwrite options.num_cpus with the nb_cores value
  77 options.num_cpus = nb_cores
  78
  79 # system simulated
  80 system = System(cpu = cpus,
  81                 funcmem = SimpleMemory(in_addr_map = False),
  82                 funcbus = NoncoherentBus(),
  83                 physmem = SimpleMemory())
  84
  85 Ruby.create_system(options, system)
  86
  87 assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
  88
  89 for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
  90      #
  91      # Tie the cpu test and functional ports to the ruby cpu ports and
  92      # physmem, respectively
  93      #
  94      cpus[i].test = ruby_port.slave
  95      cpus[i].functional = system.funcbus.slave
  96
  97      #
  98      # Since the memtester is incredibly bursty, increase the deadlock
  99      # threshold to 1 million cycles
 100      #
 101      ruby_port.deadlock_threshold = 1000000
 102
 103      #
 104      # Ruby doesn't need the backing image of memory when running with
 105      # the tester.
 106      #
 107      ruby_port.access_phys_mem = False
 108
 109 # connect reference memory to funcbus
 110 system.funcmem.port = system.funcbus.master
 111
 112 # -----------------------
 113 # run simulation
 114 # -----------------------
 115
 116 root = Root(full_system = False, system = system)
 117 root.system.mem_mode = 'timing'
 118
 119 # Not much point in this being higher than the L1 latency
 120 m5.ticks.setGlobalFrequency('1ns')