tests/configs/memtest.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 from Caches import *
  33
  34 #MAX CORES IS 8 with the fals sharing method
  35 nb_cores = 8
  36 cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
  37
  38 # system simulated
  39 system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
  40                 funcbus = NoncoherentBus(),
  41                 physmem = SimpleMemory(),
  42                 membus = CoherentBus(clock="1GHz", width=16))
  43
  44 # l2cache & bus
  45 system.toL2Bus = CoherentBus(clock="2GHz", width=16)
  46 system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8)
  47 system.l2c.cpu_side = system.toL2Bus.master
  48
  49 # connect l2c to membus
  50 system.l2c.mem_side = system.membus.slave
  51
  52 # add L1 caches
  53 for cpu in cpus:
  54     cpu.l1c = L1Cache(size = '32kB', assoc = 4)
  55     cpu.l1c.cpu_side = cpu.test
  56     cpu.l1c.mem_side = system.toL2Bus.slave
  57     system.funcbus.slave = cpu.functional
  58
  59 system.system_port = system.membus.slave
  60
  61 # connect reference memory to funcbus
  62 system.funcmem.port = system.funcbus.master
  63
  64 # connect memory to membus
  65 system.physmem.port = system.membus.master
  66
  67
  68 # -----------------------
  69 # run simulation
  70 # -----------------------
  71
  72 root = Root( full_system = False, system = system )
  73 root.system.mem_mode = 'timing'
  74 #root.trace.flags="Cache CachePort MemoryAccess"
  75 #root.trace.cycle=1
  76