tests/configs/memtest.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31
  32 # --------------------
  33 # Base L1 Cache
  34 # ====================
  35
  36 class L1(BaseCache):
  37     latency = '1ns'
  38     block_size = 64
  39     mshrs = 12
  40     tgts_per_mshr = 8
  41     is_top_level = True
  42
  43 # ----------------------
  44 # Base L2 Cache
  45 # ----------------------
  46
  47 class L2(BaseCache):
  48     block_size = 64
  49     latency = '10ns'
  50     mshrs = 92
  51     tgts_per_mshr = 16
  52     write_buffers = 8
  53
  54 #MAX CORES IS 8 with the fals sharing method
  55 nb_cores = 8
  56 cpus = [ MemTest() for i in xrange(nb_cores) ]
  57
  58 # system simulated
  59 system = System(cpu = cpus, funcmem = PhysicalMemory(),
  60                 physmem = PhysicalMemory(),
  61                 membus = Bus(clock="500GHz", width=16))
  62
  63 # l2cache & bus
  64 system.toL2Bus = Bus(clock="500GHz", width=16)
  65 system.l2c = L2(size='64kB', assoc=8)
  66 system.l2c.cpu_side = system.toL2Bus.master
  67
  68 # connect l2c to membus
  69 system.l2c.mem_side = system.membus.slave
  70
  71 # add L1 caches
  72 for cpu in cpus:
  73     cpu.l1c = L1(size = '32kB', assoc = 4)
  74     cpu.l1c.cpu_side = cpu.test
  75     cpu.l1c.mem_side = system.toL2Bus.slave
  76     system.funcmem.port = cpu.functional
  77
  78 system.system_port = system.membus.slave
  79
  80 # connect memory to membus
  81 system.physmem.port = system.membus.master
  82
  83
  84 # -----------------------
  85 # run simulation
  86 # -----------------------
  87
  88 root = Root( full_system = False, system = system )
  89 root.system.mem_mode = 'timing'
  90 #root.trace.flags="Cache CachePort MemoryAccess"
  91 #root.trace.cycle=1
  92