tests/configs/memtest.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31
  32 # --------------------
  33 # Base L1 Cache
  34 # ====================
  35
  36 class L1(BaseCache):
  37     latency = '1ns'
  38     block_size = 64
  39     mshrs = 12
  40     tgts_per_mshr = 8
  41
  42 # ----------------------
  43 # Base L2 Cache
  44 # ----------------------
  45
  46 class L2(BaseCache):
  47     block_size = 64
  48     latency = '10ns'
  49     mshrs = 92
  50     tgts_per_mshr = 16
  51     write_buffers = 8
  52
  53 #MAX CORES IS 8 with the fals sharing method
  54 nb_cores = 8
  55 cpus = [ MemTest() for i in xrange(nb_cores) ]
  56
  57 # system simulated
  58 system = System(cpu = cpus, funcmem = PhysicalMemory(),
  59                 physmem = PhysicalMemory(),
  60                 membus = Bus(clock="500GHz", width=16))
  61
  62 # l2cache & bus
  63 system.toL2Bus = Bus(clock="500GHz", width=16)
  64 system.l2c = L2(size='64kB', assoc=8)
  65 system.l2c.cpu_side = system.toL2Bus.port
  66
  67 # connect l2c to membus
  68 system.l2c.mem_side = system.membus.port
  69
  70 # add L1 caches
  71 for cpu in cpus:
  72     cpu.l1c = L1(size = '32kB', assoc = 4)
  73     cpu.l1c.cpu_side = cpu.test
  74     cpu.l1c.mem_side = system.toL2Bus.port
  75     system.funcmem.port = cpu.functional
  76
  77 # connect memory to membus
  78 system.physmem.port = system.membus.port
  79
  80
  81 # -----------------------
  82 # run simulation
  83 # -----------------------
  84
  85 root = Root( system = system )
  86 root.system.mem_mode = 'timing'
  87 #root.trace.flags="Cache CachePort MemoryAccess"
  88 #root.trace.cycle=1
  89