1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Ron Dreslinski
30 from m5
.objects
import *
33 cpus
= [ DerivO3CPU(cpu_id
=i
) for i
in range(nb_cores
) ]
36 ruby_memory
= ruby_config
.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores
)
39 system
= System(cpu
= cpus
, physmem
= ruby_memory
, membus
= SystemXBar(),
41 clk_domain
= SrcClockDomain(clock
= '1GHz'))
43 # Create a seperate clock domain for components that should run at
45 system
.cpu_clk_domain
= SrcClockDomain(clock
= '2GHz')
48 # create the interrupt controller
49 cpu
.createInterruptController()
50 cpu
.connectAllPorts(system
.membus
)
51 # All cpus are associated with cpu_clk_domain
52 cpu
.clk_domain
= system
.cpu_clk_domain
54 # connect memory to membus
55 system
.physmem
.port
= system
.membus
.master
57 # Connect the system port for loading of binaries etc
58 system
.system_port
= system
.membus
.slave
60 # -----------------------
62 # -----------------------
64 root
= Root(full_system
= False, system
= system
)
65 root
.system
.mem_mode
= 'timing'