tests/configs/o3-timing-mp-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31
  32 nb_cores = 4
  33 cpus = [ DerivO3CPU(cpu_id=i) for i in range(nb_cores) ]
  34
  35 import ruby_config
  36 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
  37
  38 # system simulated
  39 system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
  40                 mem_mode = "timing",
  41                 clk_domain = SrcClockDomain(clock = '1GHz'))
  42
  43 # Create a seperate clock domain for components that should run at
  44 # CPUs frequency
  45 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
  46
  47 for cpu in cpus:
  48     # create the interrupt controller
  49     cpu.createInterruptController()
  50     cpu.connectAllPorts(system.membus)
  51     # All cpus are associated with cpu_clk_domain
  52     cpu.clk_domain = system.cpu_clk_domain
  53
  54 # connect memory to membus
  55 system.physmem.port = system.membus.master
  56
  57 # Connect the system port for loading of binaries etc
  58 system.system_port = system.membus.slave
  59
  60 # -----------------------
  61 # run simulation
  62 # -----------------------
  63
  64 root = Root(full_system = False, system = system)
  65 root.system.mem_mode = 'timing'