tests/configs/o3-timing-mp-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 m5.util.addToPath('../configs/topologies')
  33
  34 nb_cores = 4
  35 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
  36
  37 import ruby_config
  38 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
  39
  40 # system simulated
  41 system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
  42                 mem_mode = "timing",
  43                 clk_domain = SrcClockDomain(clock = '1GHz'))
  44
  45 # Create a seperate clock domain for components that should run at
  46 # CPUs frequency
  47 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
  48
  49 for cpu in cpus:
  50     # create the interrupt controller
  51     cpu.createInterruptController()
  52     cpu.connectAllPorts(system.membus)
  53     # All cpus are associated with cpu_clk_domain
  54     cpu.clk_domain = system.cpu_clk_domain
  55
  56 # connect memory to membus
  57 system.physmem.port = system.membus.master
  58
  59 # Connect the system port for loading of binaries etc
  60 system.system_port = system.membus.slave
  61
  62 # -----------------------
  63 # run simulation
  64 # -----------------------
  65
  66 root = Root(full_system = False, system = system)
  67 root.system.mem_mode = 'timing'