tests/configs/o3-timing-mp.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
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   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32
  33 # --------------------
  34 # Base L1 Cache
  35 # ====================
  36
  37 class L1(BaseCache):
  38     hit_latency = '1ns'
  39     response_latency = '1ns'
  40     block_size = 64
  41     mshrs = 4
  42     tgts_per_mshr = 20
  43     is_top_level = True
  44
  45 # ----------------------
  46 # Base L2 Cache
  47 # ----------------------
  48
  49 class L2(BaseCache):
  50     block_size = 64
  51     hit_latency = '10ns'
  52     response_latency = '10ns'
  53     mshrs = 92
  54     tgts_per_mshr = 16
  55     write_buffers = 8
  56
  57 nb_cores = 4
  58 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
  59
  60 # system simulated
  61 system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
  62
  63 # l2cache & bus
  64 system.toL2Bus = CoherentBus()
  65 system.l2c = L2(size='4MB', assoc=8)
  66 system.l2c.cpu_side = system.toL2Bus.master
  67
  68 # connect l2c to membus
  69 system.l2c.mem_side = system.membus.slave
  70
  71 # add L1 caches
  72 for cpu in cpus:
  73     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
  74                                 L1(size = '32kB', assoc = 4))
  75     # create the interrupt controller
  76     cpu.createInterruptController()
  77     # connect cpu level-1 caches to shared level-2 cache
  78     cpu.connectAllPorts(system.toL2Bus, system.membus)
  79     cpu.clock = '2GHz'
  80
  81 # connect memory to membus
  82 system.physmem.port = system.membus.master
  83
  84 # connect system port to membus
  85 system.system_port = system.membus.slave
  86
  87 # -----------------------
  88 # run simulation
  89 # -----------------------
  90
  91 root = Root( full_system = False, system = system )
  92 root.system.mem_mode = 'timing'
  93 #root.trace.flags="Bus Cache"
  94 #root.trace.flags = "BusAddrRanges"