tests/configs/o3-timing-mp.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
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  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 m5.AddToPath('../configs/common')
  32
  33 # --------------------
  34 # Base L1 Cache
  35 # ====================
  36
  37 class L1(BaseCache):
  38     latency = 1
  39     block_size = 64
  40     mshrs = 4
  41     tgts_per_mshr = 8
  42     protocol = CoherenceProtocol(protocol='moesi')
  43
  44 # ----------------------
  45 # Base L2 Cache
  46 # ----------------------
  47
  48 class L2(BaseCache):
  49     block_size = 64
  50     latency = 100
  51     mshrs = 92
  52     tgts_per_mshr = 16
  53     write_buffers = 8
  54
  55 nb_cores = 4
  56 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
  57
  58 # system simulated
  59 system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
  60 Bus())
  61
  62 # l2cache & bus
  63 system.toL2Bus = Bus()
  64 system.l2c = L2(size='4MB', assoc=8)
  65 system.l2c.cpu_side = system.toL2Bus.port
  66
  67 # connect l2c to membus
  68 system.l2c.mem_side = system.membus.port
  69
  70 # add L1 caches
  71 for cpu in cpus:
  72     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
  73                                 L1(size = '32kB', assoc = 4))
  74     # connect cpu level-1 caches to shared level-2 cache
  75     cpu.connectMemPorts(system.toL2Bus)
  76     cpu.clock = '2GHz'
  77
  78 # connect memory to membus
  79 system.physmem.port = system.membus.port
  80
  81
  82 # -----------------------
  83 # run simulation
  84 # -----------------------
  85
  86 root = Root( system = system )
  87 root.system.mem_mode = 'timing'
  88 #root.trace.flags="Bus Cache"
  89 #root.trace.flags = "BusAddrRanges"