tests/configs/o3-timing-mp.py

   1 # Copyright (c) 2006 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
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  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 m5.AddToPath('../configs/common')
  32 from FullO3Config import *
  33
  34 # --------------------
  35 # Base L1 Cache
  36 # ====================
  37
  38 class L1(BaseCache):
  39     latency = 1
  40     block_size = 64
  41     mshrs = 4
  42     tgts_per_mshr = 8
  43     protocol = CoherenceProtocol(protocol='moesi')
  44
  45 # ----------------------
  46 # Base L2 Cache
  47 # ----------------------
  48
  49 class L2(BaseCache):
  50     block_size = 64
  51     latency = 100
  52     mshrs = 92
  53     tgts_per_mshr = 16
  54     write_buffers = 8
  55
  56 nb_cores = 4
  57 cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
  58
  59 # system simulated
  60 system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
  61 Bus())
  62
  63 # l2cache & bus
  64 system.toL2Bus = Bus()
  65 system.l2c = L2(size='4MB', assoc=8)
  66 system.l2c.cpu_side = system.toL2Bus.port
  67
  68 # connect l2c to membus
  69 system.l2c.mem_side = system.membus.port
  70
  71 # add L1 caches
  72 for cpu in cpus:
  73     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
  74                                 L1(size = '32kB', assoc = 4))
  75     cpu.mem = cpu.dcache
  76     # connect cpu level-1 caches to shared level-2 cache
  77     cpu.connectMemPorts(system.toL2Bus)
  78
  79 # connect memory to membus
  80 system.physmem.port = system.membus.port
  81
  82
  83 # -----------------------
  84 # run simulation
  85 # -----------------------
  86
  87 root = Root( system = system )
  88 root.system.mem_mode = 'timing'
  89 #root.trace.flags="Bus Cache"
  90 #root.trace.flags = "BusAddrRanges"