tests/configs/o3-timing-mp.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 from Caches import *
  33
  34 nb_cores = 4
  35 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
  36
  37 # system simulated
  38 system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
  39
  40 # l2cache & bus
  41 system.toL2Bus = CoherentBus(clock = '2GHz')
  42 system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
  43 system.l2c.cpu_side = system.toL2Bus.master
  44
  45 # connect l2c to membus
  46 system.l2c.mem_side = system.membus.slave
  47
  48 # add L1 caches
  49 for cpu in cpus:
  50     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
  51                                 L1(size = '32kB', assoc = 4))
  52     # create the interrupt controller
  53     cpu.createInterruptController()
  54     # connect cpu level-1 caches to shared level-2 cache
  55     cpu.connectAllPorts(system.toL2Bus, system.membus)
  56     cpu.clock = '2GHz'
  57
  58 # connect memory to membus
  59 system.physmem.port = system.membus.master
  60
  61 # connect system port to membus
  62 system.system_port = system.membus.slave
  63
  64 # -----------------------
  65 # run simulation
  66 # -----------------------
  67
  68 root = Root( full_system = False, system = system )
  69 root.system.mem_mode = 'timing'
  70 #root.trace.flags="Bus Cache"
  71 #root.trace.flags = "BusAddrRanges"