0fe23d1ee8c37585c0ece06a224116526014625e
1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Steve Reinhardt
30 from m5
.objects
import *
31 m5
.util
.addToPath('../configs/common')
32 from Benchmarks
import SysConfig
37 # --------------------
39 # ====================
48 # ----------------------
50 # ----------------------
59 # ---------------------
60 # Page table walker cache
61 # ---------------------
62 class PageTableWalkerCache(BaseCache
):
70 # ---------------------
72 # ---------------------
73 class IOCache(BaseCache
):
80 addr_range
= AddrRange(0, size
=mem_size
)
81 forward_snoops
= False
84 cpu
= DerivO3CPU(cpu_id
=0)
86 mdesc
= SysConfig(disk
= 'linux-x86.img')
87 system
= FSConfig
.makeLinuxX86System('timing', mdesc
=mdesc
)
88 system
.kernel
= FSConfig
.binary('x86_64-vmlinux-2.6.22.9')
89 system
.iocache
= IOCache(addr_range
=mem_size
)
90 system
.iocache
.cpu_side
= system
.iobus
.port
91 system
.iocache
.mem_side
= system
.membus
.port
95 system
.toL2Bus
= Bus()
97 #connect up the l2 cache
98 system
.l2c
= L2(size
='4MB', assoc
=8)
99 system
.l2c
.cpu_side
= system
.toL2Bus
.port
100 system
.l2c
.mem_side
= system
.membus
.port
102 #connect up the cpu and l1s
103 cpu
.addPrivateSplitL1Caches(L1(size
= '32kB', assoc
= 1),
104 L1(size
= '32kB', assoc
= 4),
105 PageTableWalkerCache(),
106 PageTableWalkerCache())
107 # connect cpu level-1 caches to shared level-2 cache
108 cpu
.connectAllPorts(system
.toL2Bus
, system
.membus
)
111 root
= Root(system
=system
)
112 m5
.ticks
.setGlobalFrequency('1THz')