tests/configs/pc-o3-timing.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 from Benchmarks import SysConfig
  33 import FSConfig
  34
  35 mem_size = '128MB'
  36
  37 # --------------------
  38 # Base L1 Cache
  39 # ====================
  40
  41 class L1(BaseCache):
  42     hit_latency = '1ns'
  43     response_latency = '1ns'
  44     block_size = 64
  45     mshrs = 4
  46     tgts_per_mshr = 20
  47     is_top_level = True
  48
  49 # ----------------------
  50 # Base L2 Cache
  51 # ----------------------
  52
  53 class L2(BaseCache):
  54     block_size = 64
  55     hit_latency = '10ns'
  56     response_latency = '10ns'
  57     mshrs = 92
  58     tgts_per_mshr = 16
  59     write_buffers = 8
  60
  61 # ---------------------
  62 # Page table walker cache
  63 # ---------------------
  64 class PageTableWalkerCache(BaseCache):
  65     assoc = 2
  66     block_size = 64
  67     hit_latency = '1ns'
  68     response_latency = '1ns'
  69     mshrs = 10
  70     size = '1kB'
  71     tgts_per_mshr = 12
  72
  73 # ---------------------
  74 # I/O Cache
  75 # ---------------------
  76 class IOCache(BaseCache):
  77     assoc = 8
  78     block_size = 64
  79     hit_latency = '50ns'
  80     response_latency = '50ns'
  81     mshrs = 20
  82     size = '1kB'
  83     tgts_per_mshr = 12
  84     addr_ranges = [AddrRange(0, size=mem_size)]
  85     forward_snoops = False
  86
  87 #cpu
  88 cpu = DerivO3CPU(cpu_id=0)
  89 #the system
  90 mdesc = SysConfig(disk = 'linux-x86.img')
  91 system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
  92 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
  93 system.iocache = IOCache()
  94 system.iocache.cpu_side = system.iobus.master
  95 system.iocache.mem_side = system.membus.slave
  96
  97 system.cpu = cpu
  98 #create the l1/l2 bus
  99 system.toL2Bus = CoherentBus()
 100
 101 #connect up the l2 cache
 102 system.l2c = L2(size='4MB', assoc=8)
 103 system.l2c.cpu_side = system.toL2Bus.master
 104 system.l2c.mem_side = system.membus.slave
 105
 106 #connect up the cpu and l1s
 107 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 108                             L1(size = '32kB', assoc = 4),
 109                             PageTableWalkerCache(),
 110                             PageTableWalkerCache())
 111 # create the interrupt controller
 112 cpu.createInterruptController()
 113 # connect cpu level-1 caches to shared level-2 cache
 114 cpu.connectAllPorts(system.toL2Bus, system.membus)
 115 cpu.clock = '2GHz'
 116
 117 root = Root(full_system=True, system=system)
 118 m5.ticks.setGlobalFrequency('1THz')
 119