tests/configs/pc-o3-timing.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 from Benchmarks import SysConfig
  33 import FSConfig
  34
  35 mem_size = '128MB'
  36
  37 # --------------------
  38 # Base L1 Cache
  39 # ====================
  40
  41 class L1(BaseCache):
  42     latency = '1ns'
  43     block_size = 64
  44     mshrs = 4
  45     tgts_per_mshr = 20
  46     is_top_level = True
  47
  48 # ----------------------
  49 # Base L2 Cache
  50 # ----------------------
  51
  52 class L2(BaseCache):
  53     block_size = 64
  54     latency = '10ns'
  55     mshrs = 92
  56     tgts_per_mshr = 16
  57     write_buffers = 8
  58
  59 # ---------------------
  60 # Page table walker cache
  61 # ---------------------
  62 class PageTableWalkerCache(BaseCache):
  63     assoc = 2
  64     block_size = 64
  65     latency = '1ns'
  66     mshrs = 10
  67     size = '1kB'
  68     tgts_per_mshr = 12
  69
  70 # ---------------------
  71 # I/O Cache
  72 # ---------------------
  73 class IOCache(BaseCache):
  74     assoc = 8
  75     block_size = 64
  76     latency = '50ns'
  77     mshrs = 20
  78     size = '1kB'
  79     tgts_per_mshr = 12
  80     addr_range = AddrRange(0, size=mem_size)
  81     forward_snoops = False
  82
  83 #cpu
  84 cpu = DerivO3CPU(cpu_id=0)
  85 #the system
  86 mdesc = SysConfig(disk = 'linux-x86.img')
  87 system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
  88 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
  89 system.iocache = IOCache(addr_range=mem_size)
  90 system.iocache.cpu_side = system.iobus.port
  91 system.iocache.mem_side = system.membus.port
  92
  93 system.cpu = cpu
  94 #create the l1/l2 bus
  95 system.toL2Bus = Bus()
  96
  97 #connect up the l2 cache
  98 system.l2c = L2(size='4MB', assoc=8)
  99 system.l2c.cpu_side = system.toL2Bus.port
 100 system.l2c.mem_side = system.membus.port
 101
 102 #connect up the cpu and l1s
 103 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 104                             L1(size = '32kB', assoc = 4),
 105                             PageTableWalkerCache(),
 106                             PageTableWalkerCache())
 107 # connect cpu level-1 caches to shared level-2 cache
 108 cpu.connectAllPorts(system.toL2Bus, system.membus)
 109 cpu.clock = '2GHz'
 110
 111 root = Root(full_system=True, system=system)
 112 m5.ticks.setGlobalFrequency('1THz')
 113