tests/configs/pc-simple-timing-ruby.py

   1 # Copyright (c) 2012 Mark D. Hill and David A. Wood
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Nilay Vaish
  28
  29 import m5, os, optparse, sys
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/')
  32 from common.Benchmarks import SysConfig
  33 from common import FSConfig
  34 from ruby import Ruby
  35 from common import Options
  36
  37 # Add the ruby specific and protocol specific options
  38 parser = optparse.OptionParser()
  39 Options.addCommonOptions(parser)
  40 Ruby.define_options(parser)
  41 (options, args) = parser.parse_args()
  42
  43 # Set the default cache size and associativity to be very small to encourage
  44 # races between requests and writebacks.
  45 options.l1d_size="32kB"
  46 options.l1i_size="32kB"
  47 options.l2_size="4MB"
  48 options.l1d_assoc=2
  49 options.l1i_assoc=2
  50 options.l2_assoc=2
  51 options.num_cpus = 2
  52
  53 #the system
  54 mdesc = SysConfig(disk = 'linux-x86.img')
  55 system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
  56                                      mdesc=mdesc, Ruby=True)
  57 # Dummy voltage domain for all our clock domains
  58 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
  59
  60 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
  61 system.clk_domain = SrcClockDomain(clock = '1GHz',
  62                                    voltage_domain = system.voltage_domain)
  63 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
  64                                        voltage_domain = system.voltage_domain)
  65 system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
  66               for i in range(options.num_cpus)]
  67
  68 Ruby.create_system(options, True, system, system.iobus, system._dma_ports)
  69
  70 # Create a seperate clock domain for Ruby
  71 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
  72                                         voltage_domain = system.voltage_domain)
  73
  74 # Connect the ruby io port to the PIO bus,
  75 # assuming that there is just one such port.
  76 system.iobus.master = system.ruby._io_port.slave
  77
  78 for (i, cpu) in enumerate(system.cpu):
  79     # create the interrupt controller
  80     cpu.createInterruptController()
  81     # Tie the cpu ports to the correct ruby system ports
  82     cpu.icache_port = system.ruby._cpu_ports[i].slave
  83     cpu.dcache_port = system.ruby._cpu_ports[i].slave
  84     cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
  85     cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
  86
  87     cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
  88     cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
  89     cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
  90
  91 root = Root(full_system = True, system = system)
  92 m5.ticks.setGlobalFrequency('1THz')