tests/configs/pc-simple-timing-ruby.py

   1 # Copyright (c) 2012 Mark D. Hill and David A. Wood
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Nilay Vaish
  28
  29 import m5, os, optparse, sys
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 from Benchmarks import SysConfig
  33 import FSConfig
  34
  35 m5.util.addToPath('../configs/ruby')
  36 m5.util.addToPath('../configs/topologies')
  37 import Ruby
  38 import Options
  39
  40 # Add the ruby specific and protocol specific options
  41 parser = optparse.OptionParser()
  42 Options.addCommonOptions(parser)
  43 Ruby.define_options(parser)
  44 (options, args) = parser.parse_args()
  45
  46 # Set the default cache size and associativity to be very small to encourage
  47 # races between requests and writebacks.
  48 options.l1d_size="32kB"
  49 options.l1i_size="32kB"
  50 options.l2_size="4MB"
  51 options.l1d_assoc=2
  52 options.l1i_assoc=2
  53 options.l2_assoc=2
  54 options.num_cpus = 2
  55
  56 #the system
  57 mdesc = SysConfig(disk = 'linux-x86.img')
  58 system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
  59                                      mdesc=mdesc, Ruby=True)
  60 # Dummy voltage domain for all our clock domains
  61 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
  62
  63 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
  64 system.clk_domain = SrcClockDomain(clock = '1GHz',
  65                                    voltage_domain = system.voltage_domain)
  66 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
  67                                        voltage_domain = system.voltage_domain)
  68 system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
  69               for i in xrange(options.num_cpus)]
  70
  71 Ruby.create_system(options, True, system, system.iobus, system._dma_ports)
  72
  73 # Create a seperate clock domain for Ruby
  74 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
  75                                         voltage_domain = system.voltage_domain)
  76
  77 # Connect the ruby io port to the PIO bus,
  78 # assuming that there is just one such port.
  79 system.iobus.master = system.ruby._io_port.slave
  80
  81 for (i, cpu) in enumerate(system.cpu):
  82     # create the interrupt controller
  83     cpu.createInterruptController()
  84     # Tie the cpu ports to the correct ruby system ports
  85     cpu.icache_port = system.ruby._cpu_ports[i].slave
  86     cpu.dcache_port = system.ruby._cpu_ports[i].slave
  87     cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
  88     cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
  89
  90     cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
  91     cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
  92     cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
  93
  94 root = Root(full_system = True, system = system)
  95 m5.ticks.setGlobalFrequency('1THz')