1 # Copyright (c) 2012 Mark D. Hill and David A. Wood
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Nilay Vaish
29 import m5
, os
, optparse
, sys
30 from m5
.objects
import *
31 m5
.util
.addToPath('../configs/common')
32 from Benchmarks
import SysConfig
35 m5
.util
.addToPath('../configs/ruby')
36 m5
.util
.addToPath('../configs/topologies')
40 # Add the ruby specific and protocol specific options
41 parser
= optparse
.OptionParser()
42 Options
.addCommonOptions(parser
)
43 Ruby
.define_options(parser
)
44 (options
, args
) = parser
.parse_args()
46 # Set the default cache size and associativity to be very small to encourage
47 # races between requests and writebacks.
48 options
.l1d_size
="32kB"
49 options
.l1i_size
="32kB"
57 mdesc
= SysConfig(disk
= 'linux-x86.img')
58 system
= FSConfig
.makeLinuxX86System('timing', options
.num_cpus
,
59 mdesc
=mdesc
, Ruby
=True)
61 system
.kernel
= FSConfig
.binary('x86_64-vmlinux-2.6.22.9.smp')
62 system
.clk_domain
= SrcClockDomain(clock
= '1GHz')
63 system
.cpu_clk_domain
= SrcClockDomain(clock
= '2GHz')
64 system
.cpu
= [TimingSimpleCPU(cpu_id
=i
, clk_domain
= system
.cpu_clk_domain
)
65 for i
in xrange(options
.num_cpus
)]
67 Ruby
.create_system(options
, system
, system
.piobus
, system
._dma
_ports
)
69 # Create a seperate clock domain for Ruby
70 system
.ruby
.clk_domain
= SrcClockDomain(clock
= options
.ruby_clock
)
72 for (i
, cpu
) in enumerate(system
.cpu
):
73 # create the interrupt controller
74 cpu
.createInterruptController()
75 # Tie the cpu ports to the correct ruby system ports
76 cpu
.icache_port
= system
.ruby
._cpu
_ruby
_ports
[i
].slave
77 cpu
.dcache_port
= system
.ruby
._cpu
_ruby
_ports
[i
].slave
78 cpu
.itb
.walker
.port
= system
.ruby
._cpu
_ruby
_ports
[i
].slave
79 cpu
.dtb
.walker
.port
= system
.ruby
._cpu
_ruby
_ports
[i
].slave
80 cpu
.interrupts
.pio
= system
.piobus
.master
81 cpu
.interrupts
.int_master
= system
.piobus
.slave
82 cpu
.interrupts
.int_slave
= system
.piobus
.master
84 # Set access_phys_mem to True for ruby port
85 system
.ruby
._cpu
_ruby
_ports
[i
].access_phys_mem
= True
87 system
.physmem
= [DDR3_1600_x64(range = r
,
88 conf_table_reported
= True)
89 for r
in system
.mem_ranges
]
90 for i
in xrange(len(system
.physmem
)):
91 system
.physmem
[i
].port
= system
.piobus
.master
93 root
= Root(full_system
= True, system
= system
)
94 m5
.ticks
.setGlobalFrequency('1THz')