tests/configs/pc-simple-timing.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 from Benchmarks import SysConfig
  33 import FSConfig
  34
  35
  36 mem_size = '128MB'
  37
  38 # --------------------
  39 # Base L1 Cache
  40 # ====================
  41
  42 class L1(BaseCache):
  43     latency = '1ns'
  44     block_size = 64
  45     mshrs = 4
  46     tgts_per_mshr = 8
  47     is_top_level = True
  48
  49 # ----------------------
  50 # Base L2 Cache
  51 # ----------------------
  52
  53 class L2(BaseCache):
  54     block_size = 64
  55     latency = '10ns'
  56     mshrs = 92
  57     tgts_per_mshr = 16
  58     write_buffers = 8
  59
  60 # ---------------------
  61 # Page table walker cache
  62 # ---------------------
  63 class PageTableWalkerCache(BaseCache):
  64     assoc = 2
  65     block_size = 64
  66     latency = '1ns'
  67     mshrs = 10
  68     size = '1kB'
  69     tgts_per_mshr = 12
  70
  71 # ---------------------
  72 # I/O Cache
  73 # ---------------------
  74 class IOCache(BaseCache):
  75     assoc = 8
  76     block_size = 64
  77     latency = '50ns'
  78     mshrs = 20
  79     size = '1kB'
  80     tgts_per_mshr = 12
  81     addr_range = AddrRange(0, size=mem_size)
  82     forward_snoops = False
  83
  84 #cpu
  85 cpu = TimingSimpleCPU(cpu_id=0)
  86 #the system
  87 mdesc = SysConfig(disk = 'linux-x86.img')
  88 system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
  89 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
  90
  91 system.cpu = cpu
  92 #create the l1/l2 bus
  93 system.toL2Bus = Bus()
  94 system.iocache = IOCache(addr_range=mem_size)
  95 system.iocache.cpu_side = system.iobus.master
  96 system.iocache.mem_side = system.membus.slave
  97
  98
  99 #connect up the l2 cache
 100 system.l2c = L2(size='4MB', assoc=8)
 101 system.l2c.cpu_side = system.toL2Bus.master
 102 system.l2c.mem_side = system.membus.slave
 103
 104 #connect up the cpu and l1s
 105 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 106                             L1(size = '32kB', assoc = 4),
 107                             PageTableWalkerCache(),
 108                             PageTableWalkerCache())
 109 # connect cpu level-1 caches to shared level-2 cache
 110 cpu.connectAllPorts(system.toL2Bus, system.membus)
 111 cpu.clock = '2GHz'
 112
 113 root = Root(full_system=True, system=system)
 114 m5.ticks.setGlobalFrequency('1THz')
 115