1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Steve Reinhardt
30 from m5
.objects
import *
31 m5
.util
.addToPath('../configs/common')
32 from Benchmarks
import SysConfig
39 cpu
= TimingSimpleCPU(cpu_id
=0)
41 mdesc
= SysConfig(disk
= 'linux-x86.img')
42 system
= FSConfig
.makeLinuxX86System('timing', mdesc
= mdesc
)
43 system
.kernel
= FSConfig
.binary('x86_64-vmlinux-2.6.22.9')
48 system
.iocache
= IOCache(clock
= '1GHz', addr_ranges
= [AddrRange(mem_size
)])
49 system
.iocache
.cpu_side
= system
.iobus
.master
50 system
.iocache
.mem_side
= system
.membus
.slave
52 #connect up the cpu and caches
53 cpu
.addTwoLevelCacheHierarchy(L1Cache(size
= '32kB', assoc
= 1),
54 L1Cache(size
= '32kB', assoc
= 4),
55 L2Cache(size
= '4MB', assoc
= 8),
56 PageTableWalkerCache(),
57 PageTableWalkerCache())
58 # create the interrupt controller
59 cpu
.createInterruptController()
60 # connect cpu and caches to the rest of the system
61 cpu
.connectAllPorts(system
.membus
)
62 # set the cpu clock along with the caches and l1-l2 bus
65 root
= Root(full_system
=True, system
=system
)
66 m5
.ticks
.setGlobalFrequency('1THz')