tests/configs/pc-simple-timing.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 from Benchmarks import SysConfig
  33 import FSConfig
  34
  35
  36 mem_size = '128MB'
  37
  38 # --------------------
  39 # Base L1 Cache
  40 # ====================
  41
  42 class L1(BaseCache):
  43     hit_latency = '1ns'
  44     response_latency = '1ns'
  45     block_size = 64
  46     mshrs = 4
  47     tgts_per_mshr = 8
  48     is_top_level = True
  49
  50 # ----------------------
  51 # Base L2 Cache
  52 # ----------------------
  53
  54 class L2(BaseCache):
  55     block_size = 64
  56     hit_latency = '10ns'
  57     response_latency = '10ns'
  58     mshrs = 92
  59     tgts_per_mshr = 16
  60     write_buffers = 8
  61
  62 # ---------------------
  63 # Page table walker cache
  64 # ---------------------
  65 class PageTableWalkerCache(BaseCache):
  66     assoc = 2
  67     block_size = 64
  68     hit_latency = '1ns'
  69     response_latency = '1ns'
  70     mshrs = 10
  71     size = '1kB'
  72     tgts_per_mshr = 12
  73
  74 # ---------------------
  75 # I/O Cache
  76 # ---------------------
  77 class IOCache(BaseCache):
  78     assoc = 8
  79     block_size = 64
  80     hit_latency = '50ns'
  81     response_latency = '50ns'
  82     mshrs = 20
  83     size = '1kB'
  84     tgts_per_mshr = 12
  85     addr_ranges = [AddrRange(0, size=mem_size)]
  86     forward_snoops = False
  87
  88 #cpu
  89 cpu = TimingSimpleCPU(cpu_id=0)
  90 #the system
  91 mdesc = SysConfig(disk = 'linux-x86.img')
  92 system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
  93 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
  94
  95 system.cpu = cpu
  96 #create the l1/l2 bus
  97 system.toL2Bus = CoherentBus()
  98 system.iocache = IOCache()
  99 system.iocache.cpu_side = system.iobus.master
 100 system.iocache.mem_side = system.membus.slave
 101
 102
 103 #connect up the l2 cache
 104 system.l2c = L2(size='4MB', assoc=8)
 105 system.l2c.cpu_side = system.toL2Bus.master
 106 system.l2c.mem_side = system.membus.slave
 107
 108 #connect up the cpu and l1s
 109 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 110                             L1(size = '32kB', assoc = 4),
 111                             PageTableWalkerCache(),
 112                             PageTableWalkerCache())
 113 # create the interrupt controller
 114 cpu.createInterruptController()
 115 # connect cpu level-1 caches to shared level-2 cache
 116 cpu.connectAllPorts(system.toL2Bus, system.membus)
 117 cpu.clock = '2GHz'
 118
 119 root = Root(full_system=True, system=system)
 120 m5.ticks.setGlobalFrequency('1THz')
 121