CheckerCPU: Make some basic regression tests for CheckerCPU
[gem5.git] / tests / configs / realview-o3-checker.py
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36 # Authors: Geoffrey Blake
37
38 import m5
39 from m5.objects import *
40 m5.util.addToPath('../configs/common')
41 import FSConfig
42
43
44 # --------------------
45 # Base L1 Cache
46 # ====================
47
48 class L1(BaseCache):
49 latency = '1ns'
50 block_size = 64
51 mshrs = 4
52 tgts_per_mshr = 20
53 is_top_level = True
54
55 # ----------------------
56 # Base L2 Cache
57 # ----------------------
58
59 class L2(BaseCache):
60 block_size = 64
61 latency = '10ns'
62 mshrs = 92
63 tgts_per_mshr = 16
64 write_buffers = 8
65
66 # ---------------------
67 # I/O Cache
68 # ---------------------
69 class IOCache(BaseCache):
70 assoc = 8
71 block_size = 64
72 latency = '50ns'
73 mshrs = 20
74 size = '1kB'
75 tgts_per_mshr = 12
76 addr_ranges = [AddrRange(0, size='256MB')]
77 forward_snoops = False
78
79 #cpu
80 cpu = DerivO3CPU(cpu_id=0)
81 #the system
82 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
83
84 system.cpu = cpu
85 #create the l1/l2 bus
86 system.toL2Bus = Bus()
87 system.iocache = IOCache()
88 system.iocache.cpu_side = system.iobus.master
89 system.iocache.mem_side = system.membus.slave
90
91
92 #connect up the l2 cache
93 system.l2c = L2(size='4MB', assoc=8)
94 system.l2c.cpu_side = system.toL2Bus.master
95 system.l2c.mem_side = system.membus.slave
96
97 #connect up the checker
98 cpu.addCheckerCpu()
99 #connect up the cpu and l1s
100 cpu.createInterruptController()
101 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
102 L1(size = '32kB', assoc = 4))
103 # connect cpu level-1 caches to shared level-2 cache
104 cpu.connectAllPorts(system.toL2Bus, system.membus)
105 cpu.clock = '2GHz'
106
107 root = Root(full_system=True, system=system)
108 m5.ticks.setGlobalFrequency('1THz')
109