1 # Copyright (c) 2011 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Geoffrey Blake
39 from m5
.objects
import *
40 m5
.util
.addToPath('../configs/common')
44 # --------------------
46 # ====================
55 # ----------------------
57 # ----------------------
66 # ---------------------
68 # ---------------------
69 class IOCache(BaseCache
):
76 addr_ranges
= [AddrRange(0, size
='256MB')]
77 forward_snoops
= False
80 cpu
= DerivO3CPU(cpu_id
=0)
82 system
= FSConfig
.makeArmSystem('timing', "RealView_PBX", None, False)
86 system
.toL2Bus
= Bus()
87 system
.iocache
= IOCache()
88 system
.iocache
.cpu_side
= system
.iobus
.master
89 system
.iocache
.mem_side
= system
.membus
.slave
92 #connect up the l2 cache
93 system
.l2c
= L2(size
='4MB', assoc
=8)
94 system
.l2c
.cpu_side
= system
.toL2Bus
.master
95 system
.l2c
.mem_side
= system
.membus
.slave
97 #connect up the checker
99 #connect up the cpu and l1s
100 cpu
.createInterruptController()
101 cpu
.addPrivateSplitL1Caches(L1(size
= '32kB', assoc
= 1),
102 L1(size
= '32kB', assoc
= 4))
103 # connect cpu level-1 caches to shared level-2 cache
104 cpu
.connectAllPorts(system
.toL2Bus
, system
.membus
)
107 root
= Root(full_system
=True, system
=system
)
108 m5
.ticks
.setGlobalFrequency('1THz')