tests/configs/realview-o3-dual.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 import FSConfig
  33 from Benchmarks import *
  34
  35 # --------------------
  36 # Base L1 Cache
  37 # ====================
  38
  39 class L1(BaseCache):
  40     hit_latency = 2
  41     response_latency = 2
  42     block_size = 64
  43     mshrs = 4
  44     tgts_per_mshr = 20
  45     is_top_level = True
  46
  47 # ----------------------
  48 # Base L2 Cache
  49 # ----------------------
  50
  51 class L2(BaseCache):
  52     block_size = 64
  53     hit_latency = 20
  54     response_latency = 20
  55     mshrs = 92
  56     tgts_per_mshr = 16
  57     write_buffers = 8
  58
  59 # ---------------------
  60 # I/O Cache
  61 # ---------------------
  62 class IOCache(BaseCache):
  63     assoc = 8
  64     block_size = 64
  65     hit_latency = 50
  66     response_latency = 50
  67     mshrs = 20
  68     size = '1kB'
  69     tgts_per_mshr = 12
  70     addr_ranges = [AddrRange(0, size='256MB')]
  71     forward_snoops = False
  72
  73 #cpu
  74 cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
  75 #the system
  76 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
  77 system.iocache = IOCache(clock = '1GHz')
  78 system.iocache.cpu_side = system.iobus.master
  79 system.iocache.mem_side = system.membus.slave
  80
  81 system.cpu = cpus
  82 #create the l1/l2 bus
  83 system.toL2Bus = CoherentBus(clock = '2GHz')
  84
  85 #connect up the l2 cache
  86 system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
  87 system.l2c.cpu_side = system.toL2Bus.master
  88 system.l2c.mem_side = system.membus.slave
  89
  90 #connect up the cpu and l1s
  91 for c in cpus:
  92     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
  93                                 L1(size = '32kB', assoc = 4))
  94     # create the interrupt controller
  95     c.createInterruptController()
  96     # connect cpu level-1 caches to shared level-2 cache
  97     c.connectAllPorts(system.toL2Bus, system.membus)
  98     c.clock = '2GHz'
  99
 100
 101 root = Root(full_system=True, system=system)
 102 m5.ticks.setGlobalFrequency('1THz')
 103