tests/configs/realview-simple-timing.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 import FSConfig
  33
  34
  35 # --------------------
  36 # Base L1 Cache
  37 # ====================
  38
  39 class L1(BaseCache):
  40     hit_latency = '1ns'
  41     response_latency = '1ns'
  42     block_size = 64
  43     mshrs = 4
  44     tgts_per_mshr = 8
  45     is_top_level = True
  46
  47 # ----------------------
  48 # Base L2 Cache
  49 # ----------------------
  50
  51 class L2(BaseCache):
  52     block_size = 64
  53     hit_latency = '10ns'
  54     response_latency = '10ns'
  55     mshrs = 92
  56     tgts_per_mshr = 16
  57     write_buffers = 8
  58
  59 # ---------------------
  60 # I/O Cache
  61 # ---------------------
  62 class IOCache(BaseCache):
  63     assoc = 8
  64     block_size = 64
  65     hit_latency = '50ns'
  66     response_latency = '50ns'
  67     mshrs = 20
  68     size = '1kB'
  69     tgts_per_mshr = 12
  70     addr_ranges = [AddrRange(0, size='256MB')]
  71     forward_snoops = False
  72
  73 #cpu
  74 cpu = TimingSimpleCPU(cpu_id=0)
  75 #the system
  76 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
  77
  78 system.cpu = cpu
  79
  80 #create the iocache
  81 system.iocache = IOCache()
  82 system.iocache.cpu_side = system.iobus.master
  83 system.iocache.mem_side = system.membus.slave
  84
  85 #connect up the cpu and caches
  86 cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
  87                               L1(size = '32kB', assoc = 4),
  88                               L2(size = '4MB', assoc = 8))
  89 # create the interrupt controller
  90 cpu.createInterruptController()
  91 # connect cpu and caches to the rest of the system
  92 cpu.connectAllPorts(system.membus)
  93 # set the cpu clock along with the caches and l1-l2 bus
  94 cpu.clock = '2GHz'
  95
  96 root = Root(full_system=True, system=system)
  97 m5.ticks.setGlobalFrequency('1THz')
  98