tests/configs/rubytest-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Ron Dreslinski
  29 #          Brad Beckmann
  30
  31 import m5
  32 from m5.objects import *
  33 from m5.defines import buildEnv
  34 from m5.util import addToPath
  35 import os, optparse, sys
  36
  37 m5.util.addToPath('../configs/')
  38
  39 from ruby import Ruby
  40 from common import Options
  41
  42 parser = optparse.OptionParser()
  43 Options.addNoISAOptions(parser)
  44
  45 # Add the ruby specific and protocol specific options
  46 Ruby.define_options(parser)
  47
  48 (options, args) = parser.parse_args()
  49
  50 #
  51 # Set the default cache size and associativity to be very small to encourage
  52 # races between requests and writebacks.
  53 #
  54 options.l1d_size="256B"
  55 options.l1i_size="256B"
  56 options.l2_size="512B"
  57 options.l3_size="1kB"
  58 options.l1d_assoc=2
  59 options.l1i_assoc=2
  60 options.l2_assoc=2
  61 options.l3_assoc=2
  62 options.ports=32
  63
  64 # Turn on flush check for the hammer protocol
  65 check_flush = False
  66 if buildEnv['PROTOCOL'] == 'MOESI_hammer':
  67     check_flush = True
  68
  69 #
  70 # create the tester and system, including ruby
  71 #
  72 tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
  73                     wakeup_frequency = 10, num_cpus = options.num_cpus)
  74
  75 # We set the testers as cpu for ruby to find the correct clock domains
  76 # for the L1 Objects.
  77 system = System(cpu = tester)
  78
  79 # Dummy voltage domain for all our clock domains
  80 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
  81 system.clk_domain = SrcClockDomain(clock = '1GHz',
  82                                    voltage_domain = system.voltage_domain)
  83
  84 system.mem_ranges = AddrRange('256MB')
  85
  86 Ruby.create_system(options, False, system)
  87
  88 # Create a separate clock domain for Ruby
  89 system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
  90                                         voltage_domain = system.voltage_domain)
  91
  92 assert(options.num_cpus == len(system.ruby._cpu_ports))
  93
  94 tester.num_cpus = len(system.ruby._cpu_ports)
  95
  96 #
  97 # The tester is most effective when randomization is turned on and
  98 # artifical delay is randomly inserted on messages
  99 #
 100 system.ruby.randomization = True
 101
 102 for ruby_port in system.ruby._cpu_ports:
 103     #
 104     # Tie the ruby tester ports to the ruby cpu read and write ports
 105     #
 106     if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
 107         tester.cpuInstDataPort = ruby_port.slave
 108     elif ruby_port.support_data_reqs:
 109         tester.cpuDataPort = ruby_port.slave
 110     elif ruby_port.support_inst_reqs:
 111         tester.cpuInstPort = ruby_port.slave
 112
 113     # Do not automatically retry stalled Ruby requests
 114     ruby_port.no_retry_on_stall = True
 115
 116     #
 117     # Tell the sequencer this is the ruby tester so that it
 118     # copies the subblock back to the checker
 119     #
 120     ruby_port.using_ruby_tester = True
 121
 122 # -----------------------
 123 # run simulation
 124 # -----------------------
 125
 126 root = Root(full_system = False, system = system )
 127 root.system.mem_mode = 'timing'