tests: Delete authors lists from test files.
[gem5.git] / tests / configs / rubytest-ruby.py
1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
3 # All rights reserved.
4 #
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
15 #
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
28 import m5
29 from m5.objects import *
30 from m5.defines import buildEnv
31 from m5.util import addToPath
32 import os, optparse, sys
33
34 m5.util.addToPath('../configs/')
35
36 from ruby import Ruby
37 from common import Options
38
39 parser = optparse.OptionParser()
40 Options.addNoISAOptions(parser)
41
42 # Add the ruby specific and protocol specific options
43 Ruby.define_options(parser)
44
45 (options, args) = parser.parse_args()
46
47 #
48 # Set the default cache size and associativity to be very small to encourage
49 # races between requests and writebacks.
50 #
51 options.l1d_size="256B"
52 options.l1i_size="256B"
53 options.l2_size="512B"
54 options.l3_size="1kB"
55 options.l1d_assoc=2
56 options.l1i_assoc=2
57 options.l2_assoc=2
58 options.l3_assoc=2
59 options.ports=32
60
61 # Turn on flush check for the hammer protocol
62 check_flush = False
63 if buildEnv['PROTOCOL'] == 'MOESI_hammer':
64 check_flush = True
65
66 #
67 # create the tester and system, including ruby
68 #
69 tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
70 wakeup_frequency = 10, num_cpus = options.num_cpus)
71
72 # We set the testers as cpu for ruby to find the correct clock domains
73 # for the L1 Objects.
74 system = System(cpu = tester)
75
76 # Dummy voltage domain for all our clock domains
77 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
78 system.clk_domain = SrcClockDomain(clock = '1GHz',
79 voltage_domain = system.voltage_domain)
80
81 system.mem_ranges = AddrRange('256MB')
82
83 Ruby.create_system(options, False, system)
84
85 # Create a separate clock domain for Ruby
86 system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
87 voltage_domain = system.voltage_domain)
88
89 assert(options.num_cpus == len(system.ruby._cpu_ports))
90
91 tester.num_cpus = len(system.ruby._cpu_ports)
92
93 #
94 # The tester is most effective when randomization is turned on and
95 # artifical delay is randomly inserted on messages
96 #
97 system.ruby.randomization = True
98
99 for ruby_port in system.ruby._cpu_ports:
100 #
101 # Tie the ruby tester ports to the ruby cpu read and write ports
102 #
103 if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
104 tester.cpuInstDataPort = ruby_port.slave
105 elif ruby_port.support_data_reqs:
106 tester.cpuDataPort = ruby_port.slave
107 elif ruby_port.support_inst_reqs:
108 tester.cpuInstPort = ruby_port.slave
109
110 # Do not automatically retry stalled Ruby requests
111 ruby_port.no_retry_on_stall = True
112
113 #
114 # Tell the sequencer this is the ruby tester so that it
115 # copies the subblock back to the checker
116 #
117 ruby_port.using_ruby_tester = True
118
119 # -----------------------
120 # run simulation
121 # -----------------------
122
123 root = Root(full_system = False, system = system )
124 root.system.mem_mode = 'timing'