tests/configs/rubytest-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Ron Dreslinski
  29 #          Brad Beckmann
  30
  31 import m5
  32 from m5.objects import *
  33 from m5.defines import buildEnv
  34 from m5.util import addToPath
  35 import os, optparse, sys
  36
  37 # Get paths we might need.  It's expected this file is in m5/configs/example.
  38 config_path = os.path.dirname(os.path.abspath(__file__))
  39 config_root = os.path.dirname(config_path)
  40 m5_root = os.path.dirname(config_root)
  41 addToPath(config_root+'/configs/common')
  42 addToPath(config_root+'/configs/ruby')
  43 addToPath(config_root+'/configs/topologies')
  44
  45 import Ruby
  46 import Options
  47
  48 parser = optparse.OptionParser()
  49 Options.addCommonOptions(parser)
  50
  51 # Add the ruby specific and protocol specific options
  52 Ruby.define_options(parser)
  53
  54 (options, args) = parser.parse_args()
  55
  56 #
  57 # Set the default cache size and associativity to be very small to encourage
  58 # races between requests and writebacks.
  59 #
  60 options.l1d_size="256B"
  61 options.l1i_size="256B"
  62 options.l2_size="512B"
  63 options.l3_size="1kB"
  64 options.l1d_assoc=2
  65 options.l1i_assoc=2
  66 options.l2_assoc=2
  67 options.l3_assoc=2
  68
  69 # Turn on flush check for the hammer protocol
  70 check_flush = False
  71 if buildEnv['PROTOCOL'] == 'MOESI_hammer':
  72     check_flush = True
  73
  74 #
  75 # create the tester and system, including ruby
  76 #
  77 tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
  78                     wakeup_frequency = 10, num_cpus = options.num_cpus)
  79
  80 system = System(tester = tester, physmem = SimpleMemory(null = True),
  81                 clk_domain = SrcClockDomain(clock = options.sys_clock))
  82
  83 system.mem_ranges = AddrRange('256MB')
  84
  85 Ruby.create_system(options, system)
  86
  87 # Create a separate clock domain for Ruby
  88 system.ruby.clk_domain = SrcClockDomain(clock = '1GHz')
  89
  90 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
  91
  92 #
  93 # The tester is most effective when randomization is turned on and
  94 # artifical delay is randomly inserted on messages
  95 #
  96 system.ruby.randomization = True
  97
  98 for ruby_port in system.ruby._cpu_ruby_ports:
  99     #
 100     # Tie the ruby tester ports to the ruby cpu read and write ports
 101     #
 102     if ruby_port.support_data_reqs:
 103          tester.cpuDataPort = ruby_port.slave
 104     if ruby_port.support_inst_reqs:
 105          tester.cpuInstPort = ruby_port.slave
 106
 107     #
 108     # Tell the sequencer this is the ruby tester so that it
 109     # copies the subblock back to the checker
 110     #
 111     ruby_port.using_ruby_tester = True
 112
 113 # -----------------------
 114 # run simulation
 115 # -----------------------
 116
 117 root = Root(full_system = False, system = system )
 118 root.system.mem_mode = 'timing'
 119
 120 # Not much point in this being higher than the L1 latency
 121 m5.ticks.setGlobalFrequency('1ns')