tests/configs/simple-atomic-mp-ruby.py

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  26
  27 import m5
  28 from m5.objects import *
  29
  30 nb_cores = 4
  31 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in range(nb_cores) ]
  32
  33 import ruby_config
  34 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
  35
  36 # system simulated
  37 system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
  38                 clk_domain = SrcClockDomain(clock = '1GHz'))
  39
  40 # Create a seperate clock domain for components that should run at
  41 # CPUs frequency
  42 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
  43
  44 # add L1 caches
  45 for cpu in cpus:
  46     cpu.connectAllPorts(system.membus)
  47     # All cpus are associated with cpu_clk_domain
  48     cpu.clk_domain = system.cpu_clk_domain
  49
  50 # connect memory to membus
  51 system.physmem.port = system.membus.master
  52
  53 # Connect the system port for loading of binaries etc
  54 system.system_port = system.membus.slave
  55
  56 # -----------------------
  57 # run simulation
  58 # -----------------------
  59
  60 root = Root(full_system = False, system = system)
  61 root.system.mem_mode = 'atomic'