tests/configs/simple-atomic-mp.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31
  32 # --------------------
  33 # Base L1 Cache
  34 # ====================
  35
  36 class L1(BaseCache):
  37     latency = '1ns'
  38     block_size = 64
  39     mshrs = 4
  40     tgts_per_mshr = 8
  41
  42 # ----------------------
  43 # Base L2 Cache
  44 # ----------------------
  45
  46 class L2(BaseCache):
  47     block_size = 64
  48     latency = '10ns'
  49     mshrs = 92
  50     tgts_per_mshr = 16
  51     write_buffers = 8
  52
  53 nb_cores = 4
  54 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
  55
  56 # system simulated
  57 system = System(cpu = cpus, physmem = PhysicalMemory(range = AddrRange('1024MB')), membus =
  58 Bus())
  59
  60 # l2cache & bus
  61 system.toL2Bus = Bus()
  62 system.l2c = L2(size='4MB', assoc=8)
  63 system.l2c.cpu_side = system.toL2Bus.port
  64
  65 # connect l2c to membus
  66 system.l2c.mem_side = system.membus.port
  67
  68 # add L1 caches
  69 for cpu in cpus:
  70     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
  71                                 L1(size = '32kB', assoc = 4))
  72     # connect cpu level-1 caches to shared level-2 cache
  73     cpu.connectMemPorts(system.toL2Bus)
  74     cpu.clock = '2GHz'
  75
  76 # connect memory to membus
  77 system.physmem.port = system.membus.port
  78
  79
  80 # -----------------------
  81 # run simulation
  82 # -----------------------
  83
  84 root = Root( system = system )
  85 root.system.mem_mode = 'atomic'