tests/configs/simple-atomic-mp.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31
  32 # --------------------
  33 # Base L1 Cache
  34 # ====================
  35
  36 class L1(BaseCache):
  37     hit_latency = 2
  38     response_latency = 2
  39     block_size = 64
  40     mshrs = 4
  41     tgts_per_mshr = 8
  42     is_top_level = True
  43
  44 # ----------------------
  45 # Base L2 Cache
  46 # ----------------------
  47
  48 class L2(BaseCache):
  49     block_size = 64
  50     hit_latency = 20
  51     response_latency = 20
  52     mshrs = 92
  53     tgts_per_mshr = 16
  54     write_buffers = 8
  55
  56 nb_cores = 4
  57 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
  58
  59 # system simulated
  60 system = System(cpu = cpus,
  61                 physmem = SimpleMemory(range = AddrRange('1024MB')),
  62                 membus = CoherentBus())
  63
  64 # l2cache & bus
  65 system.toL2Bus = CoherentBus(clock = '2GHz')
  66 system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
  67 system.l2c.cpu_side = system.toL2Bus.master
  68
  69 # connect l2c to membus
  70 system.l2c.mem_side = system.membus.slave
  71
  72 # add L1 caches
  73 for cpu in cpus:
  74     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
  75                                 L1(size = '32kB', assoc = 4))
  76     # create the interrupt controller
  77     cpu.createInterruptController()
  78     # connect cpu level-1 caches to shared level-2 cache
  79     cpu.connectAllPorts(system.toL2Bus, system.membus)
  80     cpu.clock = '2GHz'
  81
  82 # connect memory to membus
  83 system.physmem.port = system.membus.master
  84
  85 # connect system port to membus
  86 system.system_port = system.membus.slave
  87
  88 # -----------------------
  89 # run simulation
  90 # -----------------------
  91
  92 root = Root( full_system = False, system = system )
  93 root.system.mem_mode = 'atomic'