tests/configs/simple-atomic.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31
  32 system = System(cpu = AtomicSimpleCPU(cpu_id=0),
  33                 physmem = SimpleMemory(),
  34                 membus = Bus())
  35 system.system_port = system.membus.slave
  36 system.physmem.port = system.membus.master
  37 # create the interrupt controller
  38 system.cpu.createInterruptController()
  39 system.cpu.connectAllPorts(system.membus)
  40 system.cpu.clock = '2GHz'
  41
  42 root = Root(full_system = False, system = system)