tests/configs/simple-timing-mp-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 from m5.defines import buildEnv
  32 from m5.util import addToPath
  33 import os, optparse, sys
  34
  35 # Get paths we might need
  36 config_path = os.path.dirname(os.path.abspath(__file__))
  37 config_root = os.path.dirname(config_path)
  38 m5_root = os.path.dirname(config_root)
  39 addToPath(config_root+'/configs/common')
  40 addToPath(config_root+'/configs/ruby')
  41 addToPath(config_root+'/configs/topologies')
  42
  43 import Options
  44 import Ruby
  45
  46 parser = optparse.OptionParser()
  47 Options.addCommonOptions(parser)
  48
  49 # Add the ruby specific and protocol specific options
  50 Ruby.define_options(parser)
  51
  52 (options, args) = parser.parse_args()
  53
  54 #
  55 # Set the default cache size and associativity to be very small to encourage
  56 # races between requests and writebacks.
  57 #
  58 options.l1d_size="256B"
  59 options.l1i_size="256B"
  60 options.l2_size="512B"
  61 options.l3_size="1kB"
  62 options.l1d_assoc=2
  63 options.l1i_assoc=2
  64 options.l2_assoc=2
  65 options.l3_assoc=2
  66
  67 nb_cores = 4
  68 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
  69
  70 # overwrite the num_cpus to equal nb_cores
  71 options.num_cpus = nb_cores
  72
  73 # system simulated
  74 system = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz'))
  75
  76 # Create a seperate clock domain for components that should run at
  77 # CPUs frequency
  78 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
  79
  80 Ruby.create_system(options, False, system)
  81
  82 # Create a separate clock domain for Ruby
  83 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
  84
  85 assert(options.num_cpus == len(system.ruby._cpu_ports))
  86
  87 for (i, cpu) in enumerate(system.cpu):
  88     # create the interrupt controller
  89     cpu.createInterruptController()
  90
  91     #
  92     # Tie the cpu ports to the ruby cpu ports
  93     #
  94     cpu.connectAllPorts(system.ruby._cpu_ports[i])
  95
  96 # -----------------------
  97 # run simulation
  98 # -----------------------
  99
 100 root = Root( full_system=False, system = system )
 101 root.system.mem_mode = 'timing'
 102
 103 # Not much point in this being higher than the L1 latency
 104 m5.ticks.setGlobalFrequency('1ns')