tests/configs/simple-timing-mp-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
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  11 # neither the name of the copyright holders nor the names of its
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 from m5.defines import buildEnv
  32 from m5.util import addToPath
  33 import os, optparse, sys
  34
  35 # Get paths we might need
  36 config_path = os.path.dirname(os.path.abspath(__file__))
  37 config_root = os.path.dirname(config_path)
  38 m5_root = os.path.dirname(config_root)
  39 addToPath(config_root+'/configs/common')
  40 addToPath(config_root+'/configs/ruby')
  41
  42 import Ruby
  43
  44 parser = optparse.OptionParser()
  45
  46 #
  47 # Add the ruby specific and protocol specific options
  48 #
  49 Ruby.define_options(parser)
  50
  51 execfile(os.path.join(config_root, "configs/common", "Options.py"))
  52
  53 (options, args) = parser.parse_args()
  54
  55 #
  56 # Set the default cache size and associativity to be very small to encourage
  57 # races between requests and writebacks.
  58 #
  59 options.l1d_size="256B"
  60 options.l1i_size="256B"
  61 options.l2_size="512B"
  62 options.l3_size="1kB"
  63 options.l1d_assoc=2
  64 options.l1i_assoc=2
  65 options.l2_assoc=2
  66 options.l3_assoc=2
  67
  68 nb_cores = 4
  69 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
  70
  71 # overwrite the num_cpus to equal nb_cores
  72 options.num_cpus = nb_cores
  73
  74 # system simulated
  75 system = System(cpu = cpus, physmem = PhysicalMemory())
  76
  77 Ruby.create_system(options, system)
  78
  79 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
  80
  81 for (i, cpu) in enumerate(system.cpu):
  82     #
  83     # Tie the cpu ports to the ruby cpu ports
  84     #
  85     cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
  86     cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
  87
  88 # -----------------------
  89 # run simulation
  90 # -----------------------
  91
  92 root = Root( full_system=False, system = system )
  93 root.system.mem_mode = 'timing'
  94
  95 # Not much point in this being higher than the L1 latency
  96 m5.ticks.setGlobalFrequency('1ns')