tests/configs/simple-timing-mp.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 from Caches import *
  33
  34 nb_cores = 4
  35 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
  36
  37 # system simulated
  38 system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
  39 system.clock = '1GHz'
  40
  41 # l2cache & bus
  42 system.toL2Bus = CoherentBus(clock = '2GHz')
  43 system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
  44 system.l2c.cpu_side = system.toL2Bus.master
  45
  46 # connect l2c to membus
  47 system.l2c.mem_side = system.membus.slave
  48
  49 # add L1 caches
  50 for cpu in cpus:
  51     cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
  52                                 L1Cache(size = '32kB', assoc = 4))
  53     # create the interrupt controller
  54     cpu.createInterruptController()
  55     # connect cpu level-1 caches to shared level-2 cache
  56     cpu.connectAllPorts(system.toL2Bus, system.membus)
  57     cpu.clock = '2GHz'
  58
  59 system.system_port = system.membus.slave
  60
  61 # connect memory to membus
  62 system.physmem.port = system.membus.master
  63
  64
  65 # -----------------------
  66 # run simulation
  67 # -----------------------
  68
  69 root = Root( full_system = False, system = system )
  70 root.system.mem_mode = 'timing'