tests/configs/simple-timing-mp.py

   1 # Copyright (c) 2006 The Regents of The University of Michigan
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  11 # neither the name of the copyright holders nor the names of its
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31
  32 # --------------------
  33 # Base L1 Cache
  34 # ====================
  35
  36 class L1(BaseCache):
  37     latency = 1
  38     block_size = 64
  39     mshrs = 4
  40     tgts_per_mshr = 8
  41     protocol = CoherenceProtocol(protocol='moesi')
  42
  43 # ----------------------
  44 # Base L2 Cache
  45 # ----------------------
  46
  47 class L2(BaseCache):
  48     block_size = 64
  49     latency = 100
  50     mshrs = 92
  51     tgts_per_mshr = 16
  52     write_buffers = 8
  53
  54 nb_cores = 4
  55 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
  56
  57 # system simulated
  58 system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
  59 Bus())
  60
  61 # l2cache & bus
  62 system.toL2Bus = Bus()
  63 system.l2c = L2(size='4MB', assoc=8)
  64 system.l2c.cpu_side = system.toL2Bus.port
  65
  66 # connect l2c to membus
  67 system.l2c.mem_side = system.membus.port
  68
  69 # add L1 caches
  70 for cpu in cpus:
  71     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
  72                                 L1(size = '32kB', assoc = 4))
  73     cpu.mem = cpu.dcache
  74     # connect cpu level-1 caches to shared level-2 cache
  75     cpu.connectMemPorts(system.toL2Bus)
  76
  77 # connect memory to membus
  78 system.physmem.port = system.membus.port
  79
  80
  81 # -----------------------
  82 # run simulation
  83 # -----------------------
  84
  85 root = Root( system = system )
  86 root.system.mem_mode = 'timing'