tests/configs/simple-timing-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 from m5.defines import buildEnv
  32 from m5.util import addToPath
  33 import os, optparse, sys
  34
  35 # Get paths we might need
  36 config_path = os.path.dirname(os.path.abspath(__file__))
  37 config_root = os.path.dirname(config_path)
  38 addToPath(config_root+'/configs/common')
  39 addToPath(config_root+'/configs/ruby')
  40
  41 import Ruby
  42 import Options
  43
  44 parser = optparse.OptionParser()
  45 Options.addCommonOptions(parser)
  46
  47 # Add the ruby specific and protocol specific options
  48 Ruby.define_options(parser)
  49
  50 (options, args) = parser.parse_args()
  51
  52 #
  53 # Set the default cache size and associativity to be very small to encourage
  54 # races between requests and writebacks.
  55 #
  56 options.l1d_size="256B"
  57 options.l1i_size="256B"
  58 options.l2_size="512B"
  59 options.l3_size="1kB"
  60 options.l1d_assoc=2
  61 options.l1i_assoc=2
  62 options.l2_assoc=2
  63 options.l3_assoc=2
  64
  65 # this is a uniprocessor only test
  66 options.num_cpus = 1
  67
  68 cpu = TimingSimpleCPU(cpu_id=0)
  69 system = System(cpu = cpu, physmem = PhysicalMemory())
  70
  71 Ruby.create_system(options, system)
  72
  73 assert(len(system.ruby._cpu_ruby_ports) == 1)
  74
  75 # create the interrupt controller
  76 cpu.createInterruptController()
  77
  78 #
  79 # Tie the cpu cache ports to the ruby cpu ports and
  80 # physmem, respectively
  81 #
  82 cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
  83
  84 # -----------------------
  85 # run simulation
  86 # -----------------------
  87
  88 root = Root(full_system = False, system = system)
  89 root.system.mem_mode = 'timing'
  90
  91 # Not much point in this being higher than the L1 latency
  92 m5.ticks.setGlobalFrequency('1ns')