1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Steve Reinhardt
30 from m5
.objects
import *
31 from m5
.defines
import buildEnv
32 from m5
.util
import addToPath
33 import os
, optparse
, sys
35 m5
.util
.addToPath('../configs/')
38 from common
import Options
40 parser
= optparse
.OptionParser()
41 Options
.addCommonOptions(parser
)
43 # Add the ruby specific and protocol specific options
44 Ruby
.define_options(parser
)
46 (options
, args
) = parser
.parse_args()
49 # Set the default cache size and associativity to be very small to encourage
50 # races between requests and writebacks.
52 options
.l1d_size
="256B"
53 options
.l1i_size
="256B"
54 options
.l2_size
="512B"
61 # this is a uniprocessor only test
63 cpu
= TimingSimpleCPU(cpu_id
=0)
64 system
= System(cpu
= cpu
)
66 # Dummy voltage domain for all our clock domains
67 system
.voltage_domain
= VoltageDomain(voltage
= options
.sys_voltage
)
68 system
.clk_domain
= SrcClockDomain(clock
= '1GHz',
69 voltage_domain
= system
.voltage_domain
)
71 # Create a seperate clock domain for components that should run at
73 system
.cpu
.clk_domain
= SrcClockDomain(clock
= '2GHz',
74 voltage_domain
= system
.voltage_domain
)
76 system
.mem_ranges
= AddrRange('256MB')
77 Ruby
.create_system(options
, False, system
)
79 # Create a separate clock for Ruby
80 system
.ruby
.clk_domain
= SrcClockDomain(clock
= options
.ruby_clock
,
81 voltage_domain
= system
.voltage_domain
)
83 assert(len(system
.ruby
._cpu
_ports
) == 1)
85 # create the interrupt controller
86 cpu
.createInterruptController()
89 # Tie the cpu cache ports to the ruby cpu ports and
90 # physmem, respectively
92 cpu
.connectAllPorts(system
.ruby
._cpu
_ports
[0])
94 # -----------------------
96 # -----------------------
98 root
= Root(full_system
= False, system
= system
)
99 root
.system
.mem_mode
= 'timing'