tests/configs/simple-timing-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 from m5.defines import buildEnv
  32 from m5.util import addToPath
  33 import os, optparse, sys
  34
  35 m5.util.addToPath('../configs/')
  36
  37 from ruby import Ruby
  38 from common import Options
  39
  40 parser = optparse.OptionParser()
  41 Options.addCommonOptions(parser)
  42
  43 # Add the ruby specific and protocol specific options
  44 Ruby.define_options(parser)
  45
  46 (options, args) = parser.parse_args()
  47
  48 #
  49 # Set the default cache size and associativity to be very small to encourage
  50 # races between requests and writebacks.
  51 #
  52 options.l1d_size="256B"
  53 options.l1i_size="256B"
  54 options.l2_size="512B"
  55 options.l3_size="1kB"
  56 options.l1d_assoc=2
  57 options.l1i_assoc=2
  58 options.l2_assoc=2
  59 options.l3_assoc=2
  60
  61 # this is a uniprocessor only test
  62 options.num_cpus = 1
  63 cpu = TimingSimpleCPU(cpu_id=0)
  64 system = System(cpu = cpu)
  65
  66 # Dummy voltage domain for all our clock domains
  67 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
  68 system.clk_domain = SrcClockDomain(clock = '1GHz',
  69                                    voltage_domain = system.voltage_domain)
  70
  71 # Create a seperate clock domain for components that should run at
  72 # CPUs frequency
  73 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
  74                                        voltage_domain = system.voltage_domain)
  75
  76 system.mem_ranges = AddrRange('256MB')
  77 Ruby.create_system(options, False, system)
  78
  79 # Create a separate clock for Ruby
  80 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
  81                                         voltage_domain = system.voltage_domain)
  82
  83 assert(len(system.ruby._cpu_ports) == 1)
  84
  85 # create the interrupt controller
  86 cpu.createInterruptController()
  87
  88 #
  89 # Tie the cpu cache ports to the ruby cpu ports and
  90 # physmem, respectively
  91 #
  92 cpu.connectAllPorts(system.ruby._cpu_ports[0])
  93
  94 # -----------------------
  95 # run simulation
  96 # -----------------------
  97
  98 root = Root(full_system = False, system = system)
  99 root.system.mem_mode = 'timing'