tests/configs/simple-timing-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  14 #
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  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 from m5.defines import buildEnv
  32 from m5.util import addToPath
  33 import os, optparse, sys
  34
  35 # Get paths we might need
  36 config_path = os.path.dirname(os.path.abspath(__file__))
  37 config_root = os.path.dirname(config_path)
  38 addToPath(config_root+'/configs/common')
  39 addToPath(config_root+'/configs/ruby')
  40 addToPath(config_root+'/configs/topologies')
  41
  42 import Ruby
  43 import Options
  44
  45 parser = optparse.OptionParser()
  46 Options.addCommonOptions(parser)
  47
  48 # Add the ruby specific and protocol specific options
  49 Ruby.define_options(parser)
  50
  51 (options, args) = parser.parse_args()
  52
  53 #
  54 # Set the default cache size and associativity to be very small to encourage
  55 # races between requests and writebacks.
  56 #
  57 options.l1d_size="256B"
  58 options.l1i_size="256B"
  59 options.l2_size="512B"
  60 options.l3_size="1kB"
  61 options.l1d_assoc=2
  62 options.l1i_assoc=2
  63 options.l2_assoc=2
  64 options.l3_assoc=2
  65
  66 # this is a uniprocessor only test
  67 options.num_cpus = 1
  68 cpu = TimingSimpleCPU(cpu_id=0)
  69 system = System(cpu = cpu)
  70
  71 # Dummy voltage domain for all our clock domains
  72 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
  73 system.clk_domain = SrcClockDomain(clock = '1GHz',
  74                                    voltage_domain = system.voltage_domain)
  75
  76 # Create a seperate clock domain for components that should run at
  77 # CPUs frequency
  78 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
  79                                        voltage_domain = system.voltage_domain)
  80
  81 system.mem_ranges = AddrRange('256MB')
  82 Ruby.create_system(options, False, system)
  83
  84 # Create a separate clock for Ruby
  85 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
  86                                         voltage_domain = system.voltage_domain)
  87
  88 assert(len(system.ruby._cpu_ports) == 1)
  89
  90 # create the interrupt controller
  91 cpu.createInterruptController()
  92
  93 #
  94 # Tie the cpu cache ports to the ruby cpu ports and
  95 # physmem, respectively
  96 #
  97 cpu.connectAllPorts(system.ruby._cpu_ports[0])
  98
  99 # -----------------------
 100 # run simulation
 101 # -----------------------
 102
 103 root = Root(full_system = False, system = system)
 104 root.system.mem_mode = 'timing'
 105
 106 # Not much point in this being higher than the L1 latency
 107 m5.ticks.setGlobalFrequency('1ns')