tests/configs/simple-timing-ruby.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
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  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 from m5.defines import buildEnv
  32 from m5.util import addToPath
  33 import os, optparse, sys
  34
  35 # Get paths we might need
  36 config_path = os.path.dirname(os.path.abspath(__file__))
  37 config_root = os.path.dirname(config_path)
  38 addToPath(config_root+'/configs/common')
  39 addToPath(config_root+'/configs/ruby')
  40 addToPath(config_root+'/configs/topologies')
  41
  42 import Ruby
  43 import Options
  44
  45 parser = optparse.OptionParser()
  46 Options.addCommonOptions(parser)
  47
  48 # Add the ruby specific and protocol specific options
  49 Ruby.define_options(parser)
  50
  51 (options, args) = parser.parse_args()
  52
  53 #
  54 # Set the default cache size and associativity to be very small to encourage
  55 # races between requests and writebacks.
  56 #
  57 options.l1d_size="256B"
  58 options.l1i_size="256B"
  59 options.l2_size="512B"
  60 options.l3_size="1kB"
  61 options.l1d_assoc=2
  62 options.l1i_assoc=2
  63 options.l2_assoc=2
  64 options.l3_assoc=2
  65
  66 # this is a uniprocessor only test
  67 options.num_cpus = 1
  68
  69 cpu = TimingSimpleCPU(cpu_id=0)
  70 system = System(cpu = cpu, physmem = SimpleMemory(null = True),
  71                 clk_domain = SrcClockDomain(clock = '1GHz'))
  72
  73 # Create a seperate clock domain for components that should run at
  74 # CPUs frequency
  75 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
  76
  77 system.mem_ranges = AddrRange('256MB')
  78
  79 Ruby.create_system(options, system)
  80
  81 # Create a separate clock for Ruby
  82 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
  83
  84 assert(len(system.ruby._cpu_ruby_ports) == 1)
  85
  86 # create the interrupt controller
  87 cpu.createInterruptController()
  88
  89 #
  90 # Tie the cpu cache ports to the ruby cpu ports and
  91 # physmem, respectively
  92 #
  93 cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
  94
  95 # -----------------------
  96 # run simulation
  97 # -----------------------
  98
  99 root = Root(full_system = False, system = system)
 100 root.system.mem_mode = 'timing'
 101
 102 # Not much point in this being higher than the L1 latency
 103 m5.ticks.setGlobalFrequency('1ns')