tests/configs/simple-timing.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 from Caches import *
  33
  34 cpu = TimingSimpleCPU(cpu_id=0)
  35 cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
  36                               L1Cache(size = '256kB'),
  37                               L2Cache(size = '2MB'))
  38 system = System(cpu = cpu,
  39                 physmem = SimpleMemory(),
  40                 membus = CoherentBus(),
  41                 mem_mode = "timing")
  42 system.system_port = system.membus.slave
  43 system.physmem.port = system.membus.master
  44 # create the interrupt controller
  45 cpu.createInterruptController()
  46 cpu.connectAllPorts(system.membus)
  47 cpu.clock = '2GHz'
  48
  49 root = Root(full_system=False, system = system)