mem: Allow read-only caches and check compliance
[gem5.git] / tests / configs / t1000-simple-atomic.py
1 # Copyright (c) 2007 The Regents of The University of Michigan
2 # All rights reserved.
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13 # this software without specific prior written permission.
14 #
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 #
27 # Authors: Ali Saidi
28
29 import m5
30 from m5.objects import *
31 m5.util.addToPath('../configs/common')
32 import FSConfig
33
34 system = FSConfig.makeSparcSystem('atomic')
35 system.voltage_domain = VoltageDomain()
36 system.clk_domain = SrcClockDomain(clock = '1GHz',
37 voltage_domain = system.voltage_domain)
38 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
39 voltage_domain = system.voltage_domain)
40 cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain)
41 system.cpu = cpu
42 # create the interrupt controller
43 cpu.createInterruptController()
44 cpu.connectAllPorts(system.membus)
45
46 # create the memory controllers and connect them, stick with
47 # the physmem name to avoid bumping all the reference stats
48 system.physmem = [SimpleMemory(range = r)
49 for r in system.mem_ranges]
50 for i in xrange(len(system.physmem)):
51 system.physmem[i].port = system.membus.master
52
53 root = Root(full_system=True, system=system)
54
55 m5.ticks.setGlobalFrequency('2GHz')