tests/configs/tgen-dram-ctrl.py

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  35
  36 import m5
  37 from m5.objects import *
  38
  39 # both traffic generator and communication monitor are only available
  40 # if we have protobuf support, so potentially skip this test
  41 require_sim_object("TrafficGen")
  42 require_sim_object("CommMonitor")
  43
  44 # even if this is only a traffic generator, call it cpu to make sure
  45 # the scripts are happy
  46 cpu = TrafficGen(
  47     config_file=srcpath("tests/quick/se/70.tgen/tgen-dram-ctrl.cfg"))
  48
  49 # system simulated
  50 system = System(cpu = cpu, physmem = DDR3_1600_8x8(),
  51                 membus = IOXBar(width = 16),
  52                 clk_domain = SrcClockDomain(clock = '1GHz',
  53                                             voltage_domain =
  54                                             VoltageDomain()))
  55
  56 # add a communication monitor
  57 system.monitor = CommMonitor()
  58
  59 # connect the traffic generator to the bus via a communication monitor
  60 system.cpu.port = system.monitor.slave
  61 system.monitor.master = system.membus.slave
  62
  63 # connect the system port even if it is not used in this example
  64 system.system_port = system.membus.slave
  65
  66 # connect memory to the membus
  67 system.physmem.port = system.membus.master
  68
  69 # -----------------------
  70 # run simulation
  71 # -----------------------
  72
  73 root = Root(full_system = False, system = system)
  74 root.system.mem_mode = 'timing'