1 # Copyright (c) 2012 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
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7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
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20 # neither the name of the copyright holders nor the names of its
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22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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36 # Authors: Andreas Hansson
39 from m5
.objects
import *
41 # both traffic generator and communication monitor are only available
42 # if we have protobuf support, so potentially skip this test
43 require_sim_object("TrafficGen")
44 require_sim_object("CommMonitor")
46 # even if this is only a traffic generator, call it cpu to make sure
47 # the scripts are happy
48 cpu
= TrafficGen(config_file
= "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
51 system
= System(cpu
= cpu
, physmem
= SimpleDDR3(),
52 membus
= NoncoherentBus(clock
="1GHz", width
= 16))
54 # add a communication monitor
55 system
.monitor
= CommMonitor()
57 # connect the traffic generator to the bus via a communication monitor
58 system
.cpu
.port
= system
.monitor
.slave
59 system
.monitor
.master
= system
.membus
.slave
61 # connect the system port even if it is not used in this example
62 system
.system_port
= system
.membus
.slave
64 # connect memory to the membus
65 system
.physmem
.port
= system
.membus
.master
67 # -----------------------
69 # -----------------------
71 root
= Root(full_system
= False, system
= system
)
72 root
.system
.mem_mode
= 'timing'