tests/configs/tgen-simple-mem.py

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  36 # Authors: Andreas Hansson
  37
  38 import m5
  39 from m5.objects import *
  40
  41 # both traffic generator and communication monitor are only available
  42 # if we have protobuf support, so potentially skip this test
  43 require_sim_object("TrafficGen")
  44 require_sim_object("CommMonitor")
  45
  46 # even if this is only a traffic generator, call it cpu to make sure
  47 # the scripts are happy
  48 cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
  49
  50 # system simulated
  51 system = System(cpu = cpu, physmem = SimpleMemory(),
  52                 membus = IOXBar(width = 16),
  53                 clk_domain = SrcClockDomain(clock = '1GHz',
  54                                             voltage_domain =
  55                                             VoltageDomain()))
  56
  57 # add a communication monitor, and also trace all the packets and
  58 # calculate and verify stack distance
  59 system.monitor = CommMonitor()
  60 system.monitor.trace = MemTraceProbe(trace_file = "monitor.ptrc.gz")
  61 system.monitor.stackdist = StackDistProbe(verify = True)
  62
  63 # connect the traffic generator to the bus via a communication monitor
  64 system.cpu.port = system.monitor.slave
  65 system.monitor.master = system.membus.slave
  66
  67 # connect the system port even if it is not used in this example
  68 system.system_port = system.membus.slave
  69
  70 # connect memory to the membus
  71 system.physmem.port = system.membus.master
  72
  73 # -----------------------
  74 # run simulation
  75 # -----------------------
  76
  77 root = Root(full_system = False, system = system)
  78 root.system.mem_mode = 'timing'