tests/configs/tsunami-o3-dual.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
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  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 import FSConfig
  33 from Caches import *
  34
  35 #cpu
  36 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
  37 #the system
  38 system = FSConfig.makeLinuxAlphaSystem('timing')
  39
  40 system.cpu = cpus
  41 #create the l1/l2 bus
  42 system.toL2Bus = CoherentBus(clock = '2GHz')
  43 system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
  44 system.iocache.cpu_side = system.iobus.master
  45 system.iocache.mem_side = system.membus.slave
  46
  47
  48 #connect up the l2 cache
  49 system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
  50 system.l2c.cpu_side = system.toL2Bus.master
  51 system.l2c.mem_side = system.membus.slave
  52
  53 #connect up the cpu and l1s
  54 for c in cpus:
  55     c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
  56                               L1Cache(size = '32kB', assoc = 4))
  57     # create the interrupt controller
  58     c.createInterruptController()
  59     # connect cpu level-1 caches to shared level-2 cache
  60     c.connectAllPorts(system.toL2Bus, system.membus)
  61     c.clock = '2GHz'
  62
  63 root = Root(full_system=True, system=system)
  64 m5.ticks.setGlobalFrequency('1THz')
  65