tests/configs/tsunami-simple-atomic-dual.py

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  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 import FSConfig
  33 from Caches import *
  34
  35 #cpu
  36 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
  37 #the system
  38 system = FSConfig.makeLinuxAlphaSystem('atomic')
  39 system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
  40 system.iocache.cpu_side = system.iobus.master
  41 system.iocache.mem_side = system.membus.slave
  42
  43 system.cpu = cpus
  44 #create the l1/l2 bus
  45 system.toL2Bus = CoherentBus(clock = '2GHz')
  46
  47 #connect up the l2 cache
  48 system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
  49 system.l2c.cpu_side = system.toL2Bus.master
  50 system.l2c.mem_side = system.membus.slave
  51
  52 #connect up the cpu and l1s
  53 for c in cpus:
  54     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
  55                                 L1(size = '32kB', assoc = 4))
  56     # create the interrupt controller
  57     c.createInterruptController()
  58     # connect cpu level-1 caches to shared level-2 cache
  59     c.connectAllPorts(system.toL2Bus, system.membus)
  60     c.clock = '2GHz'
  61
  62 root = Root(full_system=True, system=system)
  63 m5.ticks.setGlobalFrequency('1THz')