1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Steve Reinhardt
30 from m5
.objects
import *
31 m5
.util
.addToPath('../configs/common')
34 # --------------------
36 # ====================
40 response_latency
= '1ns'
46 # ----------------------
48 # ----------------------
53 response_latency
= '10ns'
58 # ---------------------
60 # ---------------------
61 class IOCache(BaseCache
):
65 response_latency
= '50ns'
69 addr_ranges
= [AddrRange(0, size
='8GB')]
70 forward_snoops
= False
74 cpu
= AtomicSimpleCPU(cpu_id
=0)
76 system
= FSConfig
.makeLinuxAlphaSystem('atomic')
77 system
.iocache
= IOCache()
78 system
.iocache
.cpu_side
= system
.iobus
.master
79 system
.iocache
.mem_side
= system
.membus
.slave
83 system
.toL2Bus
= CoherentBus()
85 #connect up the l2 cache
86 system
.l2c
= L2(size
='4MB', assoc
=8)
87 system
.l2c
.cpu_side
= system
.toL2Bus
.master
88 system
.l2c
.mem_side
= system
.membus
.slave
90 #connect up the cpu and l1s
91 cpu
.addPrivateSplitL1Caches(L1(size
= '32kB', assoc
= 1),
92 L1(size
= '32kB', assoc
= 4))
93 # create the interrupt controller
94 cpu
.createInterruptController()
95 # connect cpu level-1 caches to shared level-2 cache
96 cpu
.connectAllPorts(system
.toL2Bus
, system
.membus
)
99 root
= Root(full_system
=True, system
=system
)
100 m5
.ticks
.setGlobalFrequency('1THz')