tests/configs/tsunami-simple-atomic.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  26 #
  27 # Authors: Steve Reinhardt
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 import FSConfig
  33
  34 # --------------------
  35 # Base L1 Cache
  36 # ====================
  37
  38 class L1(BaseCache):
  39     latency = '1ns'
  40     block_size = 64
  41     mshrs = 4
  42     tgts_per_mshr = 8
  43     is_top_level = True
  44
  45 # ----------------------
  46 # Base L2 Cache
  47 # ----------------------
  48
  49 class L2(BaseCache):
  50     block_size = 64
  51     latency = '10ns'
  52     mshrs = 92
  53     tgts_per_mshr = 16
  54     write_buffers = 8
  55
  56 # ---------------------
  57 # I/O Cache
  58 # ---------------------
  59 class IOCache(BaseCache):
  60     assoc = 8
  61     block_size = 64
  62     latency = '50ns'
  63     mshrs = 20
  64     size = '1kB'
  65     tgts_per_mshr = 12
  66     addr_range=AddrRange(0, size='8GB')
  67     forward_snoops = False
  68     is_top_level = True
  69
  70 #cpu
  71 cpu = AtomicSimpleCPU(cpu_id=0)
  72 #the system
  73 system = FSConfig.makeLinuxAlphaSystem('atomic')
  74 system.iocache = IOCache()
  75 system.iocache.cpu_side = system.iobus.port
  76 system.iocache.mem_side = system.membus.port
  77
  78 system.cpu = cpu
  79 #create the l1/l2 bus
  80 system.toL2Bus = Bus()
  81
  82 #connect up the l2 cache
  83 system.l2c = L2(size='4MB', assoc=8)
  84 system.l2c.cpu_side = system.toL2Bus.port
  85 system.l2c.mem_side = system.membus.port
  86
  87 #connect up the cpu and l1s
  88 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
  89                             L1(size = '32kB', assoc = 4))
  90 # connect cpu level-1 caches to shared level-2 cache
  91 cpu.connectAllPorts(system.toL2Bus, system.membus)
  92 cpu.clock = '2GHz'
  93
  94 root = Root(system=system)
  95 m5.ticks.setGlobalFrequency('1THz')
  96