1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Steve Reinhardt
30 from m5
.objects
import *
31 m5
.AddToPath('../configs/common')
35 # --------------------
37 # ====================
45 # ----------------------
47 # ----------------------
56 # ---------------------
58 # ---------------------
59 class IOCache(BaseCache
):
66 mem_side_filter_ranges
=[AddrRange(0, Addr
.max)]
67 cpu_side_filter_ranges
=[AddrRange(0x8000000000, Addr
.max)]
70 cpu
= TimingSimpleCPU(cpu_id
=0)
72 system
= FSConfig
.makeLinuxAlphaSystem('timing')
76 system
.toL2Bus
= Bus()
77 system
.bridge
.filter_ranges_a
=[AddrRange(0, Addr
.max)]
78 system
.bridge
.filter_ranges_b
=[AddrRange(0, size
='8GB')]
79 system
.iocache
= IOCache()
80 system
.iocache
.cpu_side
= system
.iobus
.port
81 system
.iocache
.mem_side
= system
.membus
.port
84 #connect up the l2 cache
85 system
.l2c
= L2(size
='4MB', assoc
=8)
86 system
.l2c
.cpu_side
= system
.toL2Bus
.port
87 system
.l2c
.mem_side
= system
.membus
.port
89 #connect up the cpu and l1s
90 cpu
.addPrivateSplitL1Caches(L1(size
= '32kB', assoc
= 1),
91 L1(size
= '32kB', assoc
= 4))
92 # connect cpu level-1 caches to shared level-2 cache
93 cpu
.connectMemPorts(system
.toL2Bus
)
96 root
= Root(system
=system
)
97 m5
.ticks
.setGlobalFrequency('1THz')