tests/configs/twosys-tsunami-simple-atomic.py

   1 # Copyright (c) 2006 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
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   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Lisa Hsu
  28
  29 import m5
  30 from m5.objects import *
  31 m5.util.addToPath('../configs/common')
  32 from FSConfig import *
  33 from Benchmarks import *
  34
  35 test_sys = makeLinuxAlphaSystem('atomic',
  36                                  SysConfig('netperf-stream-client.rcS'))
  37 test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
  38 test_sys.cpu.connectAllPorts(test_sys.membus)
  39 # In contrast to the other (one-system) Tsunami configurations we do
  40 # not have an IO cache but instead rely on an IO bridge for accesses
  41 # from masters on the IO bus to the memory bus
  42 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
  43                            ranges = [AddrRange(0, '8GB')])
  44 test_sys.iobridge.slave = test_sys.iobus.master
  45 test_sys.iobridge.master = test_sys.membus.slave
  46
  47 drive_sys = makeLinuxAlphaSystem('atomic',
  48                                  SysConfig('netperf-server.rcS'))
  49 drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
  50 drive_sys.cpu.connectAllPorts(drive_sys.membus)
  51 drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
  52                             ranges = [AddrRange(0, '8GB')])
  53 drive_sys.iobridge.slave = drive_sys.iobus.master
  54 drive_sys.iobridge.master = drive_sys.membus.slave
  55
  56 root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
  57
  58 maxtick = 199999999